1. Field of the Invention
This invention relates to the field of switching voltage regulators, and particularly to circuits for reducing di/dt noise in such regulators.
2. Description of the Related Art
An inherent problem common to all switching voltage regulators is switching noise generated by cycling the regulator's switching transistor(s) on and off. This is particularly troublesome when integrating precision analog blocks on the same substrate as the regulator: it is difficult to isolate the analog blocks from the switching noise, which can disturb analog signals inductively, capacitively or resistively.
Several well-known techniques are available to reduce or prevent switching noise from affecting analog performance. For example, the physical spacing between the switching regulator and the analog blocks can be increased. However, this may consume an unacceptable amount of area on the chip. Alternatively, the regulator's switching frequency can be increased beyond the frequencies of the analog signals in the analog block. Unfortunately, this will require a very high switching frequency when used near wideband analog signals; as a result, the di/dt and dv/dt of the switched signals also increases, as does the magnitude of the switching noise. Another approach is to synchronize the switching frequency with clocks used with the precision analog blocks. However, since the energy of the switching noise is more or less distributed in each switching period, and since there are potentially multiple coupling paths, the benefit of synchronization may be limited.
A basic switching voltage regulator is illustrated in FIG. 1. A PMOS field-effect transistor (FET) 10 and an NMOS FET 12 are connected in series between a supply voltage VDD and ground. An inductor 14 is connected between the transistors' common node 16 and the regulator's output terminal OUT. A filter capacitor 18 is connected between OUT and ground, as is a load 20 to be driven by the regulator. A control circuit 22 receives feedback information (not shown) regarding the regulator's output, and cycles transistors 10 and 12 on and off alternately in each switching period to maintain an output with desired characteristics.
The regulator is typically connected to VDD and ground via respective bond wires 24 and 26, each of which has an inherent inductance. The operation of the regulator requires fast current switching; as such, bond wires 24 and 26 experience large current changes in a short time (large di/dt) in each switching period. This results in a large voltage drop being developed across the bond wires (V=L*di/dt). The source of switching transistor 12 is typically shorted to the substrate of the chip (as shown in FIG. 1), so that the voltage across bond wire 26 also appears on the substrate; this results in switching noise being injected into the substrate. Switching noise is also coupled into supply voltage VDD, but because PMOS switching transistor 10 is generally constructed within an “N-well”, with the N-well capacitively coupled to the substrate, di/dt noise in bond wire 24 mainly affects the N-well potential rather than the substrate. Thus, di/dt-induced supply noise is not as significant as di/dt-induced ground noise.
Each switching transistor has an intrinsic body diode between its drain and its substrate (and its source when shorted to the substrate as in FIG. 1); the body diode 28 for transistor 12 is shown in FIG. 1. Switching transistor 10 sets the current through ground bond wire 26, with current conducted via bond wire 26 and body diode 28 when transistor 12 is off. Thus, it is the di/dt of switching transistor 10 that determines the amplitude and duration of any di/dt-induced ground noise—typically referred to as “ground bounce”.
The di/dt of switching transistor 10 is in turn affected by the characteristics of the control signal 30 which operates it, in that di/dt will vary with the control signal's slew rate. A slow transition rate for control signal 30 reduces di/dt and thus ground bounce. However, a slow slew rate has an adverse effect on the efficiency of the regulator: a slow transition results in transistors 10 and 12 operating in a higher on-resistance region for a longer time, thus lowering efficiency.